Research

Sufficiently advanced technology is indistinguishable from magic

My research interests are broadly in the area of high fidelity system design, with specific focus on performance and reliability.

In my current role, I design high performance software by understanding nuances of the underlying hardware and by exploiting them to achieve higher performance. I lead the team working on the HEVC encoders including the open-source x265 and the value-added UHDkit.

My work at Intel focussed on inventing bleeding edge technology to deliver elevated end-user performance in next generation Intel processors. I have worked on several aspects of Intel’s 6th generation processor, code-named Skylake including pre-Silicon performance modeling, performance validation, and post-Silicon tuning.

For my PhD dissertation, I have developed a low-cost architecture-level solution called SWATthat uses a simple set of low-cost monitors to detect hardware faults by watching for anomalous software execution. SWAT’s recovery module, which handles recovery in the presence of I/O, is developed in tandem with its detectors, ensuring minimal impact on fault-free execution. SWAT also has a sophisticated diagnosis module that distinguishes between software bugs, transient hardware faults, and permanent hardware faults.

Publications

  • Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources, Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney in Proceedings of IEEE Symposium on High Performance Computer Architecture (HPCA), 2017. Winner of Best-Paper award.

  • Efficient multi-bitrate HEVC encoding for adaptive streaming, Deepthi Nandakumar, Sagar Kocheta, Kavitha Sampath, Pradeep Ramachandran, and Tom Vaughan, in Proceedings of International Broadcasters Convention (IBC) Conference, September, 2016. Also published as invited paper in SMPTE Motion Imaging Journal, Nov-Dec, 2017.

  • Efficiency vs Performance Trade-offs in the Design of an HEVC Encoder, Tom Vaughan, Deepthi Nandakumar, Pradeep Ramachandran, and Jayram Ramachandran, in proceedings of National Association of Broadcasters (NAB) Conference Conference, April, 2016.

  • Hardware Fault Recovery for I/O Intensive Applications, Pradeep Ramachandran, Siva Kumar Sastry Hari, and Sarita Adve, in ACM Transactions on Architectures and Code Optimizations (TACO), October, 2014.

  • <Title withheld for confidentiality>Pradeep Ramachandran, Anant Nori, and Aravindh V. Anantaraman, Intel Publication, 2013.

  • Relyzer: Application Resiliency Analyzer for Transient Faults, Siva kumar Sastry Hari, Sarita V. Adve, Helia Naeimi, and Pradeep Ramachandran, in IEEE Micro, special issue on the Top Picks from the 2012 Computer Architecture Conferences, vol. 33, issue 3, May – June 2013. (One of eleven papers chosen.) 

  • <Title withheld for confidentiality>, Aravindh V. Anantaraman, Pradeep Ramachandran, and Anant Nori, Intel Publication, 2012.

  • Relyzer: Exploiting Application-Level Fault Equivalence to Analyze Application Resiliency to Transient Faults, Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naeimi, and Pradeep Ramachandran, to appear in the Proceedings of Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2012. 

  • Understanding When Symptom Detectors Work by Studying Data-Only Application ValuesPradeep Ramachandran, Siva Kumar Sastry Hari, Sarita Adve, and Helia Naeimi, in the Proceedings of IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), March 2011.

  • Relyzer: Application Resiliency Analyzer for Transient Faults, Siva Kumar Sastry Hari, Helia Naeimi, Pradeep Ramachandran, and Sarita Adve, in the Proceedings of IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), March 2011.

  • Architectures for Online Error Detection and Recovery in Multicore Processors, Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel Sorin, Albert Meixner, Arijit Biswas, and Xavier Vera, to appear in the Proceedings of the Design, Automation and Test in Europe (DATE), March 2011.

  • mSWAT: Low-Cost Hardware Fault Detection and Diagnosis for Multicore Systems, Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, and Sarita V. Adve, to appear in the Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), December 2009.

  • Accurate Microarchitecture-Level Fault Modeling for Studying Hardware Faults, Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, and Sarita V. Adve, Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA), February 2009.

  • Statistical Fault InjectionPradeep Ramachandran, Prabhakar Kudva, Jeffrey Kellington, John Schumann, and Pia Sanda, In the Proceedings of the International Conference on Dependable Systems and Networks (DSN), June, 2008.

  • Trace-Based Microarchitecture-Level Diagnosis of Permanent Hardware Faults, Man-Lap Li, Pradeep Ramchandran, Swarup Kumar Sahoo, Sarita Adve, Vikram Adve, and Yuanyuan Zhou, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.

  • Using Likely Program Invariants for Hardware Reliability, Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramchandran, Sarita Adve, Vikram Adve, and Yuanyuan Zhou, Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2008.

  • Metrics for Architecture-Level Lifetime Reliability AnalysisPradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers, and Jayanth Srinivasan to appear in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) April 2008.

  • SWAT: An Error Resilient System, Man-Lap Li, Pradeep Ramchandran, Sarita Adve, Vikram Adve, and Yuanyuan Zhou , to appear in the Fourth Workshop on Silicon Errors in Logic – System Effects (SELSE – IV), March 2008.

  • Understanding the Propagation of Hard Errors to Software and Implications for Resilient System Design, Man-Lap Li, Pradeep Ramchandran, Swarup Kumar Sahoo, Sarita Adve, Vikram Adve, and Yuanyuan Zhou , Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008.

  • Towards a Hardware-Software Co-designed Resilient System, Man-Lap Li, Pradeep Ramachandran, Sarita Adve, Vikram Adve and Yuanyuan Zhou , Third Workshop on Silicon Errors in Logic – System Effects (SELSE – III), April 2007.